Мерцает LCD SBLCDA4 на MSP430?

Question

[ftp27]

Как уже понятно их сабжа, у меня некоторые проблемы с наладкой дисплея на MSP430. Этот дисплей, SBLCDA4, используется в отладочной плате MSP-EXP430FG4618, правда МК у меня MSP430F4784. Как раз именно по схеме данной отладочной платы я и собрал схему для своего проекта, но, к несчастью, дисплей довольно таки ощутимо мерцает:


Когда все это у меня висело на проводах, я списывал подобные глюки на наводки, да и времени не было уже с этим разбираться, нужно было как можно быстрее заказывать платы. И вот они пришли, но проблема не исправилась. Пробовал массу прошивок, и естественно, примеры от TI подготовленные точно к этому дисплею.

Вот этот код должен был бы зажечь все сегменты дисплея:

#include "msp430.h"
void main(void)
{
int i;
WDTCTL = WDTPW + WDTHOLD;                               
FLL_CTL0 |= XCAP10PF;                                   
LCDACTL = LCDON + LCD4MUX + LCDFREQ_128;
LCDAPCTL0 = LCDS0+LCDS4+LCDS8+LCDS12+LCDS16+LCDS20;
P5SEL = BIT2+BIT3+BIT4;                         
for( i = 0; i < 11; i ++)
{
         LCDMEM[i] = 0xFF;                                              
}

_BIS_SR(LPM3_bits);                                     
}

Он их конечно зажигает, но без должной скорости, создавая мерцания как на анимации выше.

После нескольких тщетных попыток что либо сделать с программной стороны, я решил посмотреть что находится на ногах дисплея. Ткнул осциллограф на ногу COM3:


Выглядит не очень правильно. И вновь я начал изучать схему тестовой платы, и приметил один конденсатор на 10uF, который ставится на ногу LCDCAP. Так как керамики такого номинала нет, то пришлось ткнуть туда электролитический. Результат не заставил себя ждать:


На осциллографе, конечно, видно изменения, но вот на дисплее изменения не очень заметны. Все так же мерцает… Подскажите, пожалуйста, что же можно с этим поделать…

UPD: Снял показатели с двух ножек. COM3[Желтый] и COM2[Синий]

UDP2:Кстати. В документации приведена осциллограмма нужного режима. Похоже на то, что я на данный момент имею


UDP3: В результате долгих подборов, все же было выявлено необходимое кол-во сегментов которые должны были бы быть задействованы в проекте. С этим набором ничего не мерцает. Поэтому было решено так это и оставить

Comments

[nerudo]

А не затруднит ссылку на этот документ дать? А то в том, что нашлось никаких диаграмм не было. Мне уже просто интересно стало, как это в принципе работает.

Answer 1

[nerudo]

Я может чего-то не понимаю, но com0 вроде как цифровой сигнал выбора и должен пребывать в состоянии либо нуля либо единицы. У вас же на нем как минимум 4 разных уровня (очень красивых, что странно). Может с этого надо начать. Хотя я могу и ошибаться, т.к. никогда с подобными индикаторами не работал, а даташит какой-то совсем никакой…

Comments

[ftp27]

Мне тоже так казалось. Но я не знаю что тут поделать

[nerudo]

Как вариант — несколько выходов у вас оказались спаяны вместе, за счет этого и получается такая лесенка, т.е. проблемы монтажа (либо схемы). Было бы полезно пронаблюдать эти сигналы на чистых, никуда не припаянных выходах МК, если вдруг у вас есть такая плата.

[ftp27]

К несчастью, не могу посмотреть, т.к. печатная плата уже вся спаяна. Но могу точно заверить, что ножки нигде не спаяны между собой.

[nerudo]

Еще вариант — попытаться осмысленно зажечь какой-нибудь один элемент. Если загорится нужный, то не знаю. А вот если нет, то возможно неправильно подключен весь индикатор (ну например вверх ногами или зеркально ноги перепутаны или еще что).

[ftp27]

Один сегмент зажегся, да и ко всему этому частота увеличилась.
ссылка на даташит на русском: тык

[ftp27]

Странно. Чем меньше сегментов задействовано, тем выше частота

[ftp27]

Один сегмент:

Все сегменты

Answer 2

[PM1630]

Ни разу не сталкивался.
Возможно глупое предположение…

Но судя по этому
Board.h:
#define LCD_TEST 1 // Set to 1 to include LCD test functions

и этому LCD.h
#if LCD_TEST > 0 extern void testAll(void); extern void testSymbol(void); extern void testArrow(void); extern void testFunc(void); extern void testBatt(void); extern void testSigLvl(void); extern void testPwrLvl(void); extern void testSpecialChar(void); extern void testChar(void); #endif // LCD_TEST

По умолчанию там похоже тест запускается, который всеми элементами индикатора моргает.
И что-то очень похожее мне видится на видео…
Не? LCD_TEST в нуле?

Comments

[ftp27]

К сожалению, у меня нет таких библиотек. Но в тех, что подключены LCD_TEST нет

[PM1630]

Тогда — ой.
Я их (Board и LCD) вытащил по первой же ссылке — www.ti.com/tool/msp-exp430fg4618 Get Software
Из архива — slac129c.zip \ slac129 \ LCD

А можно узнать, какие библиотеки используются у Вас?

[ftp27]

Всего навсего две:

msp430.h

/*******************************************************************
*                                                                  *
* This file is a generic include file controlled by                *
* compiler/assembler IDE generated defines                         *
*                                                                  *
*******************************************************************/

#ifndef __msp430
#define __msp430

#ifndef _SYSTEM_BUILD
#pragma system_include
#endif

#if defined (__MSP430C111__)
#include "msp430x11x.h"

#elif defined (__MSP430C1111__)
#include "msp430x11x1.h"

#elif defined (__MSP430C112__)
#include "msp430x11x.h"

#elif defined (__MSP430C1121__)
#include "msp430x11x1.h"

#elif defined (__MSP430C1331__) || defined (__MSP430C1351__)
#include "msp430x13x1.h"

#elif defined (__MSP430C311S__) || defined (__MSP430C312__) || defined (__MSP430C313__) || defined (__MSP430C314__) || defined (__MSP430C315__)
#include "msp430x31x.h"

#elif defined (__MSP430C323__) || defined (__MSP430C325__)
#include "msp430x32x.h"

#elif defined (__MSP430C336__) || defined (__MSP430C337__)
#include "msp430x33x.h"

#elif defined (__MSP430C412__) || defined (__MSP430C413__)
#include "msp430x41x.h"

#elif defined (__MSP430CG4619__)
#include "msp430xG46x.h"

#elif defined (__MSP430E112__)
#include "msp430x11x.h"

#elif defined (__MSP430E313__) || defined (__MSP430E315__)
#include "msp430x31x.h"

#elif defined (__MSP430E325__)
#include "msp430x32x.h"

#elif defined (__MSP430E337__)
#include "msp430x33x.h"

#elif defined (__MSP430F110__)
#include "msp430x11x.h"

#elif defined (__MSP430F1101__) || defined (__MSP430F1101A__) || defined (__MSP430F1111__) || defined (__MSP430F1111A__)
#include "msp430x11x1.h"

#elif defined (__MSP430F112__)
#include "msp430x11x.h"

#elif defined (__MSP430F1121__) || defined (__MSP430F1121A__)
#include "msp430x11x1.h"

#elif defined (__MSP430F1122__) || defined (__MSP430F1132__)
#include "msp430x11x2.h"

#elif defined (__MSP430F122__)
#include "msp430x12x.h"

#elif defined (__MSP430F1222__)
#include "msp430x12x2.h"

#elif defined (__MSP430F123__)
#include "msp430x12x.h"

#elif defined (__MSP430F1232__)
#include "msp430x12x2.h"

#elif defined (__MSP430F133__) || defined (__MSP430F135__)
#include "msp430x13x.h"

#elif defined (__MSP430F147__) || defined (__MSP430F148__) || defined (__MSP430F149__)
#include "msp430x14x.h"

#elif defined (__MSP430F1471__) || defined (__MSP430F1481__) || defined (__MSP430F1491__)
#include "msp430x14x1.h"

#elif defined (__MSP430F155__) || defined (__MSP430F156__) || defined (__MSP430F157__)
#include "msp430x15x.h"

#elif defined (__MSP430F167__) || defined (__MSP430F168__) || defined (__MSP430F169__) || defined (__MSP430F1610__) || defined (__MSP430F1611__) || defined (__MSP430F1612__)
#include "msp430x16x.h"

#elif defined (__MSP430F2001__) || defined (__MSP430F2011__)
#include "msp430x20x1.h"

#elif defined (__MSP430F2002__) || defined (__MSP430F2012__)
#include "msp430x20x2.h"

#elif defined (__MSP430F2003__) || defined (__MSP430F2013__)
#include "msp430x20x3.h"

#elif defined (__MSP430F2035__)
#include "msp430x20x5.h"

#elif defined (__MSP430F2101__) || defined (__MSP430F2111__) || defined (__MSP430F2121__) || defined (__MSP430F2131__)
#include "msp430x21x1.h"

#elif defined (__MSP430F2112__) || defined (__MSP430F2122__) || defined (__MSP430F2132__)
#include "msp430x21x2.h"

#elif defined (__MSP430F2232__) || defined (__MSP430F2252__) || defined (__MSP430F2272__)
#include "msp430x22x2.h"

#elif defined (__MSP430F2234__) || defined (__MSP430F2254__) || defined (__MSP430F2274__)
#include "msp430x22x4.h"

#elif defined (__MSP430F2330__) || defined (__MSP430F2350__) || defined (__MSP430F2370__)
#include "msp430x23x0.h"

#elif defined (__MSP430F233__) || defined (__MSP430F235__)
#include "msp430x23x.h"

#elif defined (__MSP430F247__) || defined (__MSP430F248__) || defined (__MSP430F249__) || defined (__MSP430F2410__)
#include "msp430x24x.h"

#elif defined (__MSP430F2471__) || defined (__MSP430F2481__) || defined (__MSP430F2491__)
#include "msp430x24x1.h"

#elif defined (__MSP430F2416__) || defined (__MSP430F2417__) || defined (__MSP430F2418__) || defined (__MSP430F2419__)
#include "msp430x241x.h"

#elif defined (__MSP430F2616__) || defined (__MSP430F2617__) || defined (__MSP430F2618__) || defined (__MSP430F2619__)
#include "msp430x26x.h"

#elif defined (__MSP430F412__) || defined (__MSP430F413__)
#include "msp430x41x.h"

#elif defined (__MSP430F415__)
#include "msp430x415.h"

#elif defined (__MSP430F417__)
#include "msp430x417.h"

#elif defined (__MSP430F4132__) || defined (__MSP430F4152__)
#include "msp430x41x2.h"

#elif defined (__MSP430F423__) || defined (__MSP430F425__) || defined (__MSP430F427__) || defined (__MSP430F423A__) || defined (__MSP430F425A__) || defined (__MSP430F427A__)
#include "msp430x42x.h"

#elif defined (__MSP430F435__) || defined (__MSP430F436__) || defined (__MSP430F437__)
#include "msp430x43x.h"

#elif defined (__MSP430F4351__) || defined (__MSP430F4361__) || defined (__MSP430F4371__)
#include "msp430x43x1.h"

#elif defined (__MSP430F447__) || defined (__MSP430F448__) || defined (__MSP430F449__)
#include "msp430x44x.h"

#elif defined (__MSP430FE423__) || defined (__MSP430FE425__) || defined (__MSP430FE427__)
#include "msp430xE42x.h"

#elif defined (__MSP430FE423A__) || defined (__MSP430FE425A__) || defined (__MSP430FE427A__)
#include "msp430xE42xA.h"

#elif defined (__MSP430FE4232__) || defined (__MSP430FE4242__) || defined (__MSP430FE4252__) || defined (__MSP430FE4272__)
#include "msp430xE42x2.h"

#elif defined (__MSP430F4783__) || defined (__MSP430F4793__)
#include "msp430x47x3.h"

#elif defined (__MSP430F4784__) || defined (__MSP430F4794__)
#include "msp430x47x4.h"

#elif defined (__MSP430F47166__) || defined (__MSP430F47176__) || defined (__MSP430F47186__) || defined (__MSP430F47196__)
#include "msp430x471x6.h"

#elif defined (__MSP430F47167__) || defined (__MSP430F47177__) || defined (__MSP430F47187__) || defined (__MSP430F47197__)
#include "msp430x471x7.h"

#elif defined (__MSP430F4250__) || defined (__MSP430F4260__) || defined (__MSP430F4270__)
#include "msp430x42x0.h"

#elif defined (__MSP430FG4250__) || defined (__MSP430FG4260__) || defined (__MSP430FG4270__)
#include "msp430xG42x0.h"

#elif defined (__MSP430FW423__) || defined (__MSP430FW425__) || defined (__MSP430FW427__)
#include "msp430xW42x.h"

#elif defined (__MSP430FG437__) || defined (__MSP430FG438__) || defined (__MSP430FG439__)
#include "msp430xG43x.h"

#elif defined (__MSP430F477__) || defined (__MSP430F478__) || defined (__MSP430F479__)
#include "msp430x47x.h"

#elif defined (__MSP430FG477__) || defined (__MSP430FG478__) || defined (__MSP430FG479__)
#include "msp430xG47x.h"

#elif defined (__MSP430FG4616__) || defined (__MSP430FG4617__) || defined (__MSP430FG4618__) || defined (__MSP430FG4619__)
#include "msp430xG46x.h"

#elif defined (__XMS430F5438__) || defined (__MSP430F5418__) || defined (__MSP430F5419__) || defined (__MSP430F5435__) || defined (__MSP430F5436__) || defined (__MSP430F5437__) || defined (__MSP430F5438__)
#include "msp430x54x.h"

#elif defined (__MSP430F5418A__) || defined (__MSP430F5419A__) || defined (__MSP430F5435A__) || defined (__MSP430F5436A__) || defined (__MSP430F5437A__) || defined (__MSP430F5438A__)
#include "msp430x54xA.h"

#elif defined (__MSP430F5513__) || defined (__MSP430F5514__) || defined (__MSP430F5515__) || defined (__MSP430F5517__) || defined (__MSP430F5519__)
#include "msp430x551x.h"

#elif defined (__MSP430F5521__) || defined (__MSP430F5522__) || defined (__MSP430F5524__) || defined (__MSP430F5525__) || defined (__MSP430F5526__) || defined (__MSP430F5527__) || defined (__MSP430F5528__) || defined (__MSP430F5529__)
#include "msp430x552x.h"

#elif defined (__MSP430P112__)
#include "msp430x11x.h"

#elif defined (__MSP430P313__) || defined (__MSP430P315__) || defined (__MSP430P315S__)
#include "msp430x31x.h"

#elif defined (__MSP430P325__)
#include "msp430x32x.h"

#elif defined (__MSP430P337__)
#include "msp430x33x.h"

#elif defined (__CC430F5133__) || defined (__CC430F5135__) || defined (__CC430F5137__)
#include "cc430x513x.h"

#elif defined (__CC430F6125__) || defined (__CC430F6126__) || defined (__CC430F6127__)
#include "cc430x612x.h"

#elif defined (__CC430F6135__) || defined (__CC430F6137__)
#include "cc430x613x.h"

/********************************************************************
 *  msp430 generic
 ********************************************************************/
#elif defined (__MSP430GENERIC__)
#error "msp430 generic device does not have a default include file"

#elif defined (__MSP430XGENERIC__)
#error "msp430X generic device does not have a default include file"


/********************************************************************
 *  
 ********************************************************************/
#else
#error "Failed to match a default include file"
#endif

#endif /* #ifndef __msp430 */

msp430x47x4.h

/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430x47x4 devices.
*
* Texas Instruments, Version 1.3
*
* Rev. 1.0, Setup
* Rev. 1.1, added FCTL4 Register
* Rev. 1.2, added definitions for Interrupt Vectors xxIV
* Rev. 1.3, added LFXT1DIG
*
*
********************************************************************/

#ifndef __msp430x47x4
#define __msp430x47x4

#ifdef  __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif

#if (((__TID__ >> 8) & 0x7F) != 0x2b)     /* 0x2b = 43 dec */
#error msp430x47x4.h file for use with ICC430/A430 only
#endif


#ifdef __IAR_SYSTEMS_ICC__
#include <in430.h>
#pragma language=extended

#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;
#define DEFXC  volatile unsigned char
#define DEFXW  volatile unsigned short

#endif  /* __IAR_SYSTEMS_ICC__  */


#ifdef __IAR_SYSTEMS_ASM__
#define DEFC(name, address) sfrb name = address;
#define DEFW(name, address) sfrw name = address;

#endif /* __IAR_SYSTEMS_ASM__*/

#ifdef __cplusplus
#define READ_ONLY
#else
#define READ_ONLY const
#endif

/************************************************************
* STANDARD BITS
************************************************************/

#define BIT0                (0x0001)
#define BIT1                (0x0002)
#define BIT2                (0x0004)
#define BIT3                (0x0008)
#define BIT4                (0x0010)
#define BIT5                (0x0020)
#define BIT6                (0x0040)
#define BIT7                (0x0080)
#define BIT8                (0x0100)
#define BIT9                (0x0200)
#define BITA                (0x0400)
#define BITB                (0x0800)
#define BITC                (0x1000)
#define BITD                (0x2000)
#define BITE                (0x4000)
#define BITF                (0x8000)

/************************************************************
* STATUS REGISTER BITS
************************************************************/

#define C                   (0x0001)
#define Z                   (0x0002)
#define N                   (0x0004)
#define V                   (0x0100)
#define GIE                 (0x0008)
#define CPUOFF              (0x0010)
#define OSCOFF              (0x0020)
#define SCG0                (0x0040)
#define SCG1                (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */

#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
#define LPM0                (CPUOFF)
#define LPM1                (SCG0+CPUOFF)
#define LPM2                (SCG1+CPUOFF)
#define LPM3                (SCG1+SCG0+CPUOFF)
#define LPM4                (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */

#else /* Begin #defines for C */
#define LPM0_bits           (CPUOFF)
#define LPM1_bits           (SCG0+CPUOFF)
#define LPM2_bits           (SCG1+CPUOFF)
#define LPM3_bits           (SCG1+SCG0+CPUOFF)
#define LPM4_bits           (SCG1+SCG0+OSCOFF+CPUOFF)

#include <In430.h>

#define LPM0      _BIS_SR(LPM0_bits)     /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1      _BIS_SR(LPM1_bits)     /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2      _BIS_SR(LPM2_bits)     /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3      _BIS_SR(LPM3_bits)     /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4      _BIS_SR(LPM4_bits)     /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */

/************************************************************
* PERIPHERAL FILE MAP
************************************************************/

/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/

#define IE1_                (0x0000)  /* Interrupt Enable 1 */
DEFC(   IE1               , IE1_)
#define WDTIE               (0x01)    /* Watchdog Interrupt Enable */
#define OFIE                (0x02)    /* Osc. Fault  Interrupt Enable */
#define NMIIE               (0x10)    /* NMI Interrupt Enable */
#define ACCVIE              (0x20)    /* Flash Access Violation Interrupt Enable */

#define IFG1_               (0x0002)  /* Interrupt Flag 1 */
DEFC(   IFG1              , IFG1_)
#define WDTIFG              (0x01)    /* WDT Interrupt Flag */
#define OFIFG               (0x02)    /* Osc. Fault Interrupt Flag */
#define PORIFG              (0x04)    /* Power On Interrupt Flag */
#define RSTIFG              (0x08)    /* Reset Interrupt Flag */
#define NMIIFG              (0x10)    /* NMI Interrupt Flag */

#define IE2_                (0x0001)  /* Interrupt Enable 2 */
DEFC(   IE2               , IE2_)
#define UC0IE               IE2
#define UCA0RXIE            (0x01)
#define UCA0TXIE            (0x02)
#define UCB0RXIE            (0x04)
#define UCB0TXIE            (0x08)
#define BTIE                (0x80)

#define IFG2_               (0x0003)  /* Interrupt Flag 2 */
DEFC(   IFG2              , IFG2_)
#define UC0IFG              IFG2
#define UCA0RXIFG           (0x01)
#define UCA0TXIFG           (0x02)
#define UCB0RXIFG           (0x04)
#define UCB0TXIFG           (0x08)
#define BTIFG               (0x80)

#define UC1IE_              (0x0006)  /* USCI 1 Interrupt Enable */
DEFC(   UC1IE             , UC1IE_)
#define UCA1RXIE            (0x01)
#define UCA1TXIE            (0x02)
#define UCB1RXIE            (0x04)
#define UCB1TXIE            (0x08)

#define UC1IFG_             (0x0007)  /* ISCI 1 Interrupt Flags */
DEFC(   UC1IFG            , UC1IFG_)
#define UCA1RXIFG           (0x01)
#define UCA1TXIFG           (0x02)
#define UCB1RXIFG           (0x04)
#define UCB1TXIFG           (0x08)

/************************************************************
* BASIC TIMER
************************************************************/
#define __MSP430_HAS_BT__             /* Definition to show that Module is available */

#define BTCTL_              (0x0040)  /* Basic Timer Control */
DEFC(   BTCTL             , BTCTL_)
/* The bit names have been prefixed with "BT" */
#define BTIP0               (0x01)
#define BTIP1               (0x02)
#define BTIP2               (0x04)
#define BTFRFQ0             (0x08)
#define BTFRFQ1             (0x10)
#define BTDIV               (0x20)                     /* fCLK2 = ACLK:256 */
#define BTHOLD              (0x40)                     /* BT1 is held if this bit is set */
#define BTSSEL              (0x80)                     /* fBT = fMCLK (main clock) */

#define BTCNT1_             (0x0046)  /* Basic Timer Count 1 */
DEFC(   BTCNT1            , BTCNT1_)
#define BTCNT2_             (0x0047)  /* Basic Timer Count 2 */
DEFC(   BTCNT2            , BTCNT2_)

/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
#define BT_fCLK2_ACLK               (0x00)
#define BT_fCLK2_ACLK_DIV256        (BTDIV)
#define BT_fCLK2_MCLK               (BTSSEL)

/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2       (0x00)                    /* fINT = fCLK2:2 (default) */
#define BT_fCLK2_DIV4       (BTIP0)                   /* fINT = fCLK2:4 */
#define BT_fCLK2_DIV8       (BTIP1)                   /* fINT = fCLK2:8 */
#define BT_fCLK2_DIV16      (BTIP1+BTIP0)             /* fINT = fCLK2:16 */
#define BT_fCLK2_DIV32      (BTIP2)                   /* fINT = fCLK2:32 */
#define BT_fCLK2_DIV64      (BTIP2+BTIP0)             /* fINT = fCLK2:64 */
#define BT_fCLK2_DIV128     (BTIP2+BTIP1)             /* fINT = fCLK2:128 */
#define BT_fCLK2_DIV256     (BTIP2+BTIP1+BTIP0)       /* fINT = fCLK2:256 */
/* Frequency of LCD coded with Bits 3-4 */
#define BT_fLCD_DIV32       (0x00)                    /* fLCD = fACLK:32 (default) */
#define BT_fLCD_DIV64       (BTFRFQ0)                 /* fLCD = fACLK:64 */
#define BT_fLCD_DIV128      (BTFRFQ1)                 /* fLCD = fACLK:128 */
#define BT_fLCD_DIV256      (BTFRFQ1+BTFRFQ0)         /* fLCD = fACLK:256 */
/* LCD frequency values with fBT=fACLK */
#define BT_fLCD_1K          (0x00)                    /* fACLK:32 (default) */
#define BT_fLCD_512         (BTFRFQ0)                 /* fACLK:64 */
#define BT_fLCD_256         (BTFRFQ1)                 /* fACLK:128 */
#define BT_fLCD_128         (BTFRFQ1+BTFRFQ0)         /* fACLK:256 */
/* LCD frequency values with fBT=fMCLK */
#define BT_fLCD_31K         (BTSSEL)                  /* fMCLK:32 */
#define BT_fLCD_15_5K       (BTSSEL+BTFRFQ0)          /* fMCLK:64 */
#define BT_fLCD_7_8K        (BTSSEL+BTFRFQ1+BTFRFQ0)  /* fMCLK:256 */
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
/* fBT=fACLK is thought for longer interval times */
#define BT_ADLY_0_064       (0x00)                    /* 0.064ms interval (default) */
#define BT_ADLY_0_125       (BTIP0)                   /* 0.125ms    " */
#define BT_ADLY_0_25        (BTIP1)                   /* 0.25ms     " */
#define BT_ADLY_0_5         (BTIP1+BTIP0)             /* 0.5ms      " */
#define BT_ADLY_1           (BTIP2)                   /* 1ms        " */
#define BT_ADLY_2           (BTIP2+BTIP0)             /* 2ms        " */
#define BT_ADLY_4           (BTIP2+BTIP1)             /* 4ms        " */
#define BT_ADLY_8           (BTIP2+BTIP1+BTIP0)       /* 8ms        " */
#define BT_ADLY_16          (BTDIV)                   /* 16ms       " */
#define BT_ADLY_32          (BTDIV+BTIP0)             /* 32ms       " */
#define BT_ADLY_64          (BTDIV+BTIP1)             /* 64ms       " */
#define BT_ADLY_125         (BTDIV+BTIP1+BTIP0)       /* 125ms      " */
#define BT_ADLY_250         (BTDIV+BTIP2)             /* 250ms      " */
#define BT_ADLY_500         (BTDIV+BTIP2+BTIP0)       /* 500ms      " */
#define BT_ADLY_1000        (BTDIV+BTIP2+BTIP1)       /* 1000ms     " */
#define BT_ADLY_2000        (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms     " */
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */
/* NOTE */
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002       (BTSSEL)                  /* 0.002ms interval       *** interval times */
#define BT_MDLY_0_004       (BTSSEL+BTIP0)            /* 0.004ms    "           *** too short for */
#define BT_MDLY_0_008       (BTSSEL+BTIP1)            /* 0.008ms    "           *** interrupt */
#define BT_MDLY_0_016       (BTSSEL+BTIP1+BTIP0)      /* 0.016ms    "           *** handling */
#define BT_MDLY_0_032       (BTSSEL+BTIP2)            /* 0.032ms    " */
#define BT_MDLY_0_064       (BTSSEL+BTIP2+BTIP0)      /* 0.064ms    " */
#define BT_MDLY_0_125       (BTSSEL+BTIP2+BTIP1)      /* 0.125ms    " */
#define BT_MDLY_0_25        (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms     " */

/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
//#define BTRESET_CNT1        (BTRESET)           /* BTCNT1 is reset while BTRESET is set */
//#define BTRESET_CNT1_2      (BTRESET+BTDIV)     /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
/* this is for BT1 */
#define BTHOLD_CNT1         (BTHOLD)            /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2       (BTHOLD+BTDIV)      /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */

/* INTERRUPT CONTROL BITS */
/* #define BTIE                0x80 */
/* #define BTIFG               0x80 */

/************************************************************
* Comparator A
************************************************************/
#define __MSP430_HAS_COMPA__          /* Definition to show that Module is available */

#define CACTL1_             (0x0059)  /* Comparator A Control 1 */
DEFC(   CACTL1            , CACTL1_)
#define CACTL2_             (0x005A)  /* Comparator A Control 2 */
DEFC(   CACTL2            , CACTL2_)
#define CAPD_               (0x005B)  /* Comparator A Port Disable */
DEFC(   CAPD              , CAPD_)

#define CAIFG               (0x01)    /* Comp. A Interrupt Flag */
#define CAIE                (0x02)    /* Comp. A Interrupt Enable */
#define CAIES               (0x04)    /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON                (0x08)    /* Comp. A enable */
#define CAREF0              (0x10)    /* Comp. A Internal Reference Select 0 */
#define CAREF1              (0x20)    /* Comp. A Internal Reference Select 1 */
#define CARSEL              (0x40)    /* Comp. A Internal Reference Enable */
#define CAEX                (0x80)    /* Comp. A Exchange Inputs */

#define CAREF_0             (0x00)    /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1             (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2             (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3             (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/

#define CAOUT               (0x01)    /* Comp. A Output */
#define CAF                 (0x02)    /* Comp. A Enable Output Filter */
#define P2CA0               (0x04)    /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1               (0x08)    /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24             (0x10)
#define CACTL25             (0x20)
#define CACTL26             (0x40)
#define CACTL27             (0x80)

#define CAPD0               (0x01)    /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1               (0x02)    /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2               (0x04)    /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3               (0x08)    /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4               (0x10)    /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5               (0x20)    /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6               (0x40)    /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7               (0x80)    /* Comp. A Disable Input Buffer of Port Register .7 */

/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH2__         /* Definition to show that Module is available */

#define FCTL1_              (0x0128)  /* FLASH Control 1 */
DEFW(   FCTL1             , FCTL1_)
#define FCTL2_              (0x012A)  /* FLASH Control 2 */
DEFW(   FCTL2             , FCTL2_)
#define FCTL3_              (0x012C)  /* FLASH Control 3 */
DEFW(   FCTL3             , FCTL3_)
#define FCTL4_              (0x01BE)  /* FLASH Control 4 */
DEFW(   FCTL4             , FCTL4_)

#define FRKEY               (0x9600)  /* Flash key returned by read */
#define FWKEY               (0xA500)  /* Flash key for write */
#define FXKEY               (0x3300)  /* for use with XOR instruction */

#define ERASE               (0x0002)  /* Enable bit for Flash segment erase */
#define MERAS               (0x0004)  /* Enable bit for Flash mass erase */
#define EEI                 (0x0008)  /* Enable Erase Interrupts */
#define EEIEX               (0x0010)  /* Enable Emergency Interrupt Exit */
#define WRT                 (0x0040)  /* Enable bit for Flash write */
#define BLKWRT              (0x0080)  /* Enable bit for Flash segment write */
#define SEGWRT              (0x0080)  /* old definition */ /* Enable bit for Flash segment write */

#define FN0                 (0x0001)  /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1                 (0x0002)  /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#ifndef FN2
#define FN2                 (0x0004)
#endif
#ifndef FN3
#define FN3                 (0x0008)
#endif
#ifndef FN4
#define FN4                 (0x0010)
#endif
#define FN5                 (0x0020)
#define FSSEL0              (0x0040)  /* Flash clock select 0 */        /* to distinguish from USART SSELx */
#define FSSEL1              (0x0080)  /* Flash clock select 1 */

#define FSSEL_0             (0x0000)  /* Flash clock select: 0 - ACLK */
#define FSSEL_1             (0x0040)  /* Flash clock select: 1 - MCLK */
#define FSSEL_2             (0x0080)  /* Flash clock select: 2 - SMCLK */
#define FSSEL_3             (0x00C0)  /* Flash clock select: 3 - SMCLK */

#define BUSY                (0x0001)  /* Flash busy: 1 */
#define KEYV                (0x0002)  /* Flash Key violation flag */
#define ACCVIFG             (0x0004)  /* Flash Access violation flag */
#define WAIT                (0x0008)  /* Wait flag for segment write */
#define LOCK                (0x0010)  /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX                (0x0020)  /* Flash Emergency Exit */
#define LOCKA               (0x0040)  /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
#define FAIL                (0x0080)  /* Last Program or Erase failed */

#define MGR0                (0x0010)  /* Marginal read 0 mode. */
#define MGR1                (0x0020)  /* Marginal read 1 mode. */

/************************************************************
* SYSTEM CLOCK, FLL+
************************************************************/
#define __MSP430_HAS_FLLPLUS__        /* Definition to show that Module is available */

#define SCFI0_              (0x0050)  /* System Clock Frequency Integrator 0 */
DEFC(   SCFI0             , SCFI0_)
#define FN_2                (0x04)    /* fDCOCLK =   1.4-12MHz*/
#define FN_3                (0x08)    /* fDCOCLK =   2.2-17Mhz*/
#define FN_4                (0x10)    /* fDCOCLK =   3.2-25Mhz*/
#define FN_8                (0x20)    /* fDCOCLK =     5-40Mhz*/
#define FLLD0               (0x40)    /* Loop Divider Bit : 0 */
#define FLLD1               (0x80)    /* Loop Divider Bit : 1 */

#define FLLD_1              (0x00)    /* Multiply Selected Loop Freq. By 1 */
#define FLLD_2              (0x40)    /* Multiply Selected Loop Freq. By 2 */
#define FLLD_4              (0x80)    /* Multiply Selected Loop Freq. By 4 */
#define FLLD_8              (0xC0)    /* Multiply Selected Loop Freq. By 8 */

#define SCFI1_              (0x0051)  /* System Clock Frequency Integrator 1 */
DEFC(   SCFI1             , SCFI1_)
#define SCFQCTL_            (0x0052)  /* System Clock Frequency Control */
DEFC(   SCFQCTL           , SCFQCTL_)
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
/* #define SCFQ_32K            0x00                        fMCLK=1*fACLK       only a range from */
#define SCFQ_64K            (0x01)                     /* fMCLK=2*fACLK          1+1 to 127+1 is possible */
#define SCFQ_128K           (0x03)                     /* fMCLK=4*fACLK */
#define SCFQ_256K           (0x07)                     /* fMCLK=8*fACLK */
#define SCFQ_512K           (0x0F)                     /* fMCLK=16*fACLK */
#define SCFQ_1M             (0x1F)                     /* fMCLK=32*fACLK */
#define SCFQ_2M             (0x3F)                     /* fMCLK=64*fACLK */
#define SCFQ_4M             (0x7F)                     /* fMCLK=128*fACLK */
#define SCFQ_M              (0x80)                     /* Modulation Disable */

#define FLL_CTL0_           (0x0053)  /* FLL+ Control 0 */
DEFC(   FLL_CTL0          , FLL_CTL0_)
#define DCOF                (0x01)                     /* DCO Fault Flag */
#define LFOF                (0x02)                     /* Low Frequency Oscillator Fault Flag */
#define XT1OF               (0x04)                     /* High Frequency Oscillator 1 Fault Flag */
#define XT2OF               (0x08)                     /* High Frequency Oscillator 2 Fault Flag */
#define OSCCAP0             (0x10)                     /* XIN/XOUT Cap 0 */
#define OSCCAP1             (0x20)                     /* XIN/XOUT Cap 1 */
#define XTS_FLL             (0x40)                     /* 1: Selects high-freq. oscillator */
#define DCOPLUS             (0x80)                     /* DCO+ Enable */

#define XCAP0PF             (0x00)                     /* XIN Cap = XOUT Cap = 0pf */
#define XCAP10PF            (0x10)                     /* XIN Cap = XOUT Cap = 10pf */
#define XCAP14PF            (0x20)                     /* XIN Cap = XOUT Cap = 14pf */
#define XCAP18PF            (0x30)                     /* XIN Cap = XOUT Cap = 18pf */
#define OSCCAP_0            (0x00)                     /* XIN Cap = XOUT Cap = 0pf */
#define OSCCAP_1            (0x10)                     /* XIN Cap = XOUT Cap = 10pf */
#define OSCCAP_2            (0x20)                     /* XIN Cap = XOUT Cap = 14pf */
#define OSCCAP_3            (0x30)                     /* XIN Cap = XOUT Cap = 18pf */

#define FLL_CTL1_           (0x0054)  /* FLL+ Control 1 */
DEFC(   FLL_CTL1          , FLL_CTL1_)
#define FLL_DIV0            (0x01)                     /* FLL+ Divide Px.x/ACLK 0 */
#define FLL_DIV1            (0x02)                     /* FLL+ Divide Px.x/ACLK 1 */
#define SELS                (0x04)                     /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
#define SELM0               (0x08)                     /* MCLK Source Select 0 */
#define SELM1               (0x10)                     /* MCLK Source Select 1 */
#define XT2OFF              (0x20)                     /* High Frequency Oscillator 2 (XT2) disable */
#define SMCLKOFF            (0x40)                     /* Peripheral Module Clock (SMCLK) disable */
#define LFXT1DIG            (0x80)                     /* Enable Digital input for LF clock */

#define FLL_DIV_1           (0x00)                     /* FLL+ Divide Px.x/ACLK By 1 */
#define FLL_DIV_2           (0x01)                     /* FLL+ Divide Px.x/ACLK By 2 */
#define FLL_DIV_4           (0x02)                     /* FLL+ Divide Px.x/ACLK By 4 */
#define FLL_DIV_8           (0x03)                     /* FLL+ Divide Px.x/ACLK By 8 */

#define SELM_DCO            (0x00)                     /* Select DCO for CPU MCLK */
#define SELM_XT2            (0x10)                     /* Select XT2 for CPU MCLK */
#define SELM_A              (0x18)                     /* Select A (from LFXT1) for CPU MCLK */

#define FLL_CTL2_           (0x0055)  /* FLL+ Control 2 */
DEFC(   FLL_CTL2          , FLL_CTL2_)

#define XT2S0               (0x40)   /* Mode 0 for XT2 */
#define XT2S1               (0x80)   /* Mode 1 for XT2 */

#define XT2S_0              (0x00)   /* Mode 0 for XT2 : 0.4 - 1 MHz */
#define XT2S_1              (0x40)   /* Mode 1 for XT2 : 1 - 4 MHz */
#define XT2S_2              (0x80)   /* Mode 2 for XT2 : 2 - 16 MHz */
#define XT2S_3              (0xC0)   /* Mode 3 for XT2 : Digital input signal */

/* INTERRUPT CONTROL BITS */
/* These two bits are defined in the Special Function Registers */
/* #define OFIFG               0x02 */
/* #define OFIE                0x02 */

/************************************************************
* LCD_A
************************************************************/
#define __MSP430_HAS_LCD_A__          /* Definition to show that Module is available */

#define LCDACTL_            (0x0090)  /* LCD_A Control Register */
DEFC(   LCDACTL           , LCDACTL_)
#define LCDON               (0x01)
#define LCDSON              (0x04)
#define LCDMX0              (0x08)
#define LCDMX1              (0x10)
#define LCDFREQ0            (0x20)
#define LCDFREQ1            (0x40)
#define LCDFREQ2            (0x80)
/* Display modes coded with Bits 2-4 */
#define LCDSTATIC           (LCDSON)
#define LCD2MUX             (LCDMX0+LCDSON)
#define LCD3MUX             (LCDMX1+LCDSON)
#define LCD4MUX             (LCDMX1+LCDMX0+LCDSON)
/* Frequency select code with Bits 5-7 */
#define LCDFREQ_32          (0x00)    /* LCD Freq: ACLK divided by 32 */
#define LCDFREQ_64          (0x20)    /* LCD Freq: ACLK divided by 64 */
#define LCDFREQ_96          (0x40)    /* LCD Freq: ACLK divided by 96 */
#define LCDFREQ_128         (0x60)    /* LCD Freq: ACLK divided by 128 */
#define LCDFREQ_192         (0x80)    /* LCD Freq: ACLK divided by 192 */
#define LCDFREQ_256         (0xA0)    /* LCD Freq: ACLK divided by 256 */
#define LCDFREQ_384         (0xC0)    /* LCD Freq: ACLK divided by 384 */
#define LCDFREQ_512         (0xE0)    /* LCD Freq: ACLK divided by 512 */

#define LCDAPCTL0_          (0x00AC)  /* LCD_A Port Control Register 0 */
DEFC(   LCDAPCTL0         , LCDAPCTL0_)
#define LCDS0               (0x01)    /* LCD Segment  0 to  3 Enable. */
#define LCDS4               (0x02)    /* LCD Segment  4 to  7 Enable. */
#define LCDS8               (0x04)    /* LCD Segment  8 to 11 Enable. */
#define LCDS12              (0x08)    /* LCD Segment 12 to 15 Enable. */
#define LCDS16              (0x10)    /* LCD Segment 16 to 19 Enable. */
#define LCDS20              (0x20)    /* LCD Segment 20 to 23 Enable. */
#define LCDS24              (0x40)    /* LCD Segment 24 to 27 Enable. */
#define LCDS28              (0x80)    /* LCD Segment 28 to 31 Enable. */

#define LCDAPCTL1_          (0x00AD)  /* LCD_A Port Control Register 1 */
DEFC(   LCDAPCTL1         , LCDAPCTL1_)
#define LCDS32              (0x01)    /* LCD Segment 32 to 35 Enable. */
#define LCDS36              (0x02)    /* LCD Segment 36 to 39 Enable. */

#define LCDAVCTL0_          (0x00AE)  /* LCD_A Voltage Control Register 0 */
DEFC(   LCDAVCTL0         , LCDAVCTL0_)
#define LCD2B               (0x01)    /* Selects 1/2 bias. */
#define VLCDREF0            (0x02)    /* Selects reference voltage for regulated charge pump: 0 */
#define VLCDREF1            (0x04)    /* Selects reference voltage for regulated charge pump: 1 */
#define LCDCPEN             (0x08)    /* LCD Voltage Charge Pump Enable. */
#define VLCDEXT             (0x10)    /* Select external source for VLCD. */
#define LCDREXT             (0x20)    /* Selects external connections for LCD mid voltages. */
#define LCDR03EXT           (0x40)    /* Selects external connection for lowest LCD voltage. */

/* Reference voltage source select for the regulated charge pump */
#define VLCDREF_0           (0<<1)    /* Internal */
#define VLCDREF_1           (1<<1)    /* External */
#define VLCDREF_2           (2<<1)    /* Reserved */
#define VLCDREF_3           (3<<1)    /* Reserved */

#define LCDAVCTL1_          (0x00AF)  /* LCD_A Voltage Control Register 1 */
DEFC(   LCDAVCTL1         , LCDAVCTL1_)
#define VLCD0               (0x02)    /* VLCD select: 0 */
#define VLCD1               (0x04)    /* VLCD select: 1 */
#define VLCD2               (0x08)    /* VLCD select: 2 */
#define VLCD3               (0x10)    /* VLCD select: 3 */

/* Charge pump voltage selections */
#define VLCD_0              (0<<1)    /* Charge pump disabled */
#define VLCD_1              (1<<1)    /* VLCD = 2.60V */
#define VLCD_2              (2<<1)    /* VLCD = 2.66V */
#define VLCD_3              (3<<1)    /* VLCD = 2.72V */
#define VLCD_4              (4<<1)    /* VLCD = 2.78V */
#define VLCD_5              (5<<1)    /* VLCD = 2.84V */
#define VLCD_6              (6<<1)    /* VLCD = 2.90V */
#define VLCD_7              (7<<1)    /* VLCD = 2.96V */
#define VLCD_8              (8<<1)    /* VLCD = 3.02V */
#define VLCD_9              (9<<1)    /* VLCD = 3.08V */
#define VLCD_10             (10<<1)   /* VLCD = 3.14V */
#define VLCD_11             (11<<1)   /* VLCD = 3.20V */
#define VLCD_12             (12<<1)   /* VLCD = 3.26V */
#define VLCD_13             (12<<1)   /* VLCD = 3.32V */
#define VLCD_14             (13<<1)   /* VLCD = 3.38V */
#define VLCD_15             (15<<1)   /* VLCD = 3.44V */

#define VLCD_DISABLED       (0<<1)    /* Charge pump disabled */
#define VLCD_2_60           (1<<1)    /* VLCD = 2.60V */
#define VLCD_2_66           (2<<1)    /* VLCD = 2.66V */
#define VLCD_2_72           (3<<1)    /* VLCD = 2.72V */
#define VLCD_2_78           (4<<1)    /* VLCD = 2.78V */
#define VLCD_2_84           (5<<1)    /* VLCD = 2.84V */
#define VLCD_2_90           (6<<1)    /* VLCD = 2.90V */
#define VLCD_2_96           (7<<1)    /* VLCD = 2.96V */
#define VLCD_3_02           (8<<1)    /* VLCD = 3.02V */
#define VLCD_3_08           (9<<1)    /* VLCD = 3.08V */
#define VLCD_3_14           (10<<1)   /* VLCD = 3.14V */
#define VLCD_3_20           (11<<1)   /* VLCD = 3.20V */
#define VLCD_3_26           (12<<1)   /* VLCD = 3.26V */
#define VLCD_3_32           (12<<1)   /* VLCD = 3.32V */
#define VLCD_3_38           (13<<1)   /* VLCD = 3.38V */
#define VLCD_3_44           (15<<1)   /* VLCD = 3.44V */

#define LCDMEM_             (0x0091)  /* LCD Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define LCDMEM              (LCDMEM_) /* LCD Memory (for assembler) */
#else
#define LCDMEM              ((char*) LCDMEM_) /* LCD Memory (for C) */
#endif
#define LCDM1_              (0x0091)  /* LCD Memory 1 */
DEFC(   LCDM1             , LCDM1_)
#define LCDM2_              (0x0092)  /* LCD Memory 2 */
DEFC(   LCDM2             , LCDM2_)
#define LCDM3_              (0x0093)  /* LCD Memory 3 */
DEFC(   LCDM3             , LCDM3_)
#define LCDM4_              (0x0094)  /* LCD Memory 4 */
DEFC(   LCDM4             , LCDM4_)
#define LCDM5_              (0x0095)  /* LCD Memory 5 */
DEFC(   LCDM5             , LCDM5_)
#define LCDM6_              (0x0096)  /* LCD Memory 6 */
DEFC(   LCDM6             , LCDM6_)
#define LCDM7_              (0x0097)  /* LCD Memory 7 */
DEFC(   LCDM7             , LCDM7_)
#define LCDM8_              (0x0098)  /* LCD Memory 8 */
DEFC(   LCDM8             , LCDM8_)
#define LCDM9_              (0x0099)  /* LCD Memory 9 */
DEFC(   LCDM9             , LCDM9_)
#define LCDM10_             (0x009A)  /* LCD Memory 10 */
DEFC(   LCDM10            , LCDM10_)
#define LCDM11_             (0x009B)  /* LCD Memory 11 */
DEFC(   LCDM11            , LCDM11_)
#define LCDM12_             (0x009C)  /* LCD Memory 12 */
DEFC(   LCDM12            , LCDM12_)
#define LCDM13_             (0x009D)  /* LCD Memory 13 */
DEFC(   LCDM13            , LCDM13_)
#define LCDM14_             (0x009E)  /* LCD Memory 14 */
DEFC(   LCDM14            , LCDM14_)
#define LCDM15_             (0x009F)  /* LCD Memory 15 */
DEFC(   LCDM15            , LCDM15_)
#define LCDM16_             (0x00A0)  /* LCD Memory 16 */
DEFC(   LCDM16            , LCDM16_)
#define LCDM17_             (0x00A1)  /* LCD Memory 17 */
DEFC(   LCDM17            , LCDM17_)
#define LCDM18_             (0x00A2)  /* LCD Memory 18 */
DEFC(   LCDM18            , LCDM18_)
#define LCDM19_             (0x00A3)  /* LCD Memory 19 */
DEFC(   LCDM19            , LCDM19_)
#define LCDM20_             (0x00A4)  /* LCD Memory 20 */
DEFC(   LCDM20            , LCDM20_)

#define LCDMA               (LCDM10)  /* LCD Memory A */
#define LCDMB               (LCDM11)  /* LCD Memory B */
#define LCDMC               (LCDM12)  /* LCD Memory C */
#define LCDMD               (LCDM13)  /* LCD Memory D */
#define LCDME               (LCDM14)  /* LCD Memory E */
#define LCDMF               (LCDM15)  /* LCD Memory F */

/************************************************************
* HARDWARE MULTIPLIER 32Bit
************************************************************/
#define __MSP430_HAS_MPY32__          /* Definition to show that Module is available */

#define MPY_B_              (0x0130)  /* Multiply Unsigned/Operand 1 (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPY_B             , MPY_B_)
#endif
#define MPYS_B_             (0x0132)  /* Multiply Signed/Operand 1 (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPYS_B            , MPYS_B_)
#endif
#define MAC_B_              (0x0134)  /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MAC_B             , MAC_B_)
#endif
#define MACS_B_             (0x0136)  /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MACS_B            , MACS_B_)
#endif
#define OP2_B_              (0x0138)  /* Operand 2 (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   OP2_B             , OP2_B_)
#endif
#define MPY_                (0x0130)  /* Multiply Unsigned/Operand 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPY               , MPY_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPY_B;
  DEFXW                               MPY;
} @ 0x0130;
#endif
#define MPYS_               (0x0132)  /* Multiply Signed/Operand 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPYS              , MPYS_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPYS_B;
  DEFXW                               MPYS;
} @ 0x0132;
#endif
#define MAC_                (0x0134)  /* Multiply Unsigned and Accumulate/Operand 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MAC               , MAC_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MAC_B;
  DEFXW                               MAC;
} @ 0x0134;
#endif
#define MACS_               (0x0136)  /* Multiply Signed and Accumulate/Operand 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MACS              , MACS_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MACS_B;
  DEFXW                               MACS;
} @ 0x0136;
#endif
#define OP2_                (0x0138)  /* Operand 2 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   OP2               , OP2_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               OP2_B;
  DEFXW                               OP2;
} @ 0x0138;
#endif
#define RESLO_              (0x013A)  /* Result Low Word */
DEFW(   RESLO             , RESLO_)
#define RESHI_              (0x013C)  /* Result High Word */
DEFW(   RESHI             , RESHI_)
#define SUMEXT_             (0x013E)  /* Sum Extend */
READ_ONLY DEFW( SUMEXT         , SUMEXT_)

#define MPY32L_B_           (0x0140)  /* 32-bit operand 1 - multiply - low word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPY32L_B          , MPY32L_B_)
#endif
#define MPY32H_B_           (0x0142)  /* 32-bit operand 1 - multiply - high word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPY32H_B          , MPY32H_B_)
#endif
#define MPYS32L_B_          (0x0144)  /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPYS32L_B         , MPYS32L_B_)
#endif
#define MPYS32H_B_          (0x0146)  /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MPYS32H_B         , MPYS32H_B_)
#endif
#define MAC32L_B_           (0x0148)  /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MAC32L_B          , MAC32L_B_)
#endif
#define MAC32H_B_           (0x014A)  /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MAC32H_B          , MAC32H_B_)
#endif
#define MACS32L_B_          (0x014C)  /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MACS32L_B         , MACS32L_B_)
#endif
#define MACS32H_B_          (0x014E)  /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   MACS32H_B         , MACS32H_B_)
#endif
#define OP2L_B_             (0x0150)  /* 32-bit operand 2 - low word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   OP2L_B            , OP2L_B_)
#endif
#define OP2H_B_             (0x0152)  /* 32-bit operand 2 - high word (Byte Access) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   OP2H_B            , OP2H_B_)
#endif
#define MPY32L_             (0x0140)  /* 32-bit operand 1 - multiply - low word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPY32L            , MPY32L_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPY32L_B;
  DEFXW                               MPY32L;
} @ 0x0140;
#endif
#define MPY32H_             (0x0142)  /* 32-bit operand 1 - multiply - high word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPY32H            , MPY32H_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPY32H_B;
  DEFXW                               MPY32H;
} @ 0x0142;
#endif
#define MPYS32L_            (0x0144)  /* 32-bit operand 1 - signed multiply - low word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPYS32L           , MPYS32L_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPYS32L_B;
  DEFXW                               MPYS32L;
} @ 0x0144;
#endif
#define MPYS32H_            (0x0146)  /* 32-bit operand 1 - signed multiply - high word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MPYS32H           , MPYS32H_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MPYS32H_B;
  DEFXW                               MPYS32H;
} @ 0x0146;
#endif
#define MAC32L_             (0x0148)  /* 32-bit operand 1 - multiply accumulate - low word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MAC32L            , MAC32L_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MAC32L_B;
  DEFXW                               MAC32L;
} @ 0x0148;
#endif
#define MAC32H_             (0x014A)  /* 32-bit operand 1 - multiply accumulate - high word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MAC32H            , MAC32H_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MAC32H_B;
  DEFXW                               MAC32H;
} @ 0x014A;
#endif
#define MACS32L_            (0x014C)  /* 32-bit operand 1 - signed multiply accumulate - low word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MACS32L           , MACS32L_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MACS32L_B;
  DEFXW                               MACS32L;
} @ 0x014C;
#endif
#define MACS32H_            (0x014E)  /* 32-bit operand 1 - signed multiply accumulate - high word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   MACS32H           , MACS32H_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               MACS32H_B;
  DEFXW                               MACS32H;
} @ 0x014E;
#endif
#define OP2L_               (0x0150)  /* 32-bit operand 2 - low word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   OP2L              , OP2L_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               OP2L_B;
  DEFXW                               OP2L;
} @ 0x0150;
#endif
#define OP2H_               (0x0152)  /* 32-bit operand 2 - high word */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   OP2H              , OP2H_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  DEFXC                               OP2H_B;
  DEFXW                               OP2H;
} @ 0x0152;
#endif
#define RES0_               (0x0154)  /* 32x32-bit result 0 - least significant word */
DEFW(   RES0              , RES0_)
#define RES1_               (0x0156)  /* 32x32-bit result 1 */
DEFW(   RES1              , RES1_)
#define RES2_               (0x0158)  /* 32x32-bit result 2 */
DEFW(   RES2              , RES2_)
#define RES3_               (0x015A)  /* 32x32-bit result 3 - most significant word */
DEFW(   RES3              , RES3_)
#define MPY32CTL0_          (0x015C)  /* MPY32 Control Register 0 */
DEFW(   MPY32CTL0         , MPY32CTL0_)

#define MPYC                (0x0001)  /* Carry of the multiplier */
//#define RESERVED            (0x0002)  /* Reserved */
#define MPYFRAC             (0x0004)  /* Fractional mode */
#define MPYSAT              (0x0008)  /* Saturation mode */
#define MPYM0               (0x0010)  /* Multiplier mode Bit:0 */
#define MPYM1               (0x0020)  /* Multiplier mode Bit:1 */
#define OP1_32              (0x0040)  /* Bit-width of operand 1 0:16Bit / 1:32Bit */
#define OP2_32              (0x0080)  /* Bit-width of operand 2 0:16Bit / 1:32Bit */
#define MPYDLYWRTEN         (0x0100)  /* Delayed write enable */
#define MPYDLY32            (0x0200)  /* Delayed write mode */

#define MPYM_0              (0x0000)  /* Multiplier mode: MPY */
#define MPYM_1              (0x0010)  /* Multiplier mode: MPYS */
#define MPYM_2              (0x0020)  /* Multiplier mode: MAC */
#define MPYM_3              (0x0030)  /* Multiplier mode: MACS */
#define MPYM__MPY           (0x0000)  /* Multiplier mode: MPY */
#define MPYM__MPYS          (0x0010)  /* Multiplier mode: MPYS */
#define MPYM__MAC           (0x0020)  /* Multiplier mode: MAC */
#define MPYM__MACS          (0x0030)  /* Multiplier mode: MACS */

/************************************************************
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT1_R__        /* Definition to show that Module is available */
#define __MSP430_HAS_PORT2_R__        /* Definition to show that Module is available */

#define P1IN_               (0x0020)  /* Port 1 Input */
READ_ONLY DEFC( P1IN           , P1IN_)
#define P1OUT_              (0x0021)  /* Port 1 Output */
DEFC(   P1OUT             , P1OUT_)
#define P1DIR_              (0x0022)  /* Port 1 Direction */
DEFC(   P1DIR             , P1DIR_)
#define P1IFG_              (0x0023)  /* Port 1 Interrupt Flag */
DEFC(   P1IFG             , P1IFG_)
#define P1IES_              (0x0024)  /* Port 1 Interrupt Edge Select */
DEFC(   P1IES             , P1IES_)
#define P1IE_               (0x0025)  /* Port 1 Interrupt Enable */
DEFC(   P1IE              , P1IE_)
#define P1SEL_              (0x0026)  /* Port 1 Selection */
DEFC(   P1SEL             , P1SEL_)
#define P1REN_              (0x0027)  /* Port 1 Resistor Enable */
DEFC(   P1REN             , P1REN_)

#define P2IN_               (0x0028)  /* Port 2 Input */
READ_ONLY DEFC( P2IN           , P2IN_)
#define P2OUT_              (0x0029)  /* Port 2 Output */
DEFC(   P2OUT             , P2OUT_)
#define P2DIR_              (0x002A)  /* Port 2 Direction */
DEFC(   P2DIR             , P2DIR_)
#define P2IFG_              (0x002B)  /* Port 2 Interrupt Flag */
DEFC(   P2IFG             , P2IFG_)
#define P2IES_              (0x002C)  /* Port 2 Interrupt Edge Select */
DEFC(   P2IES             , P2IES_)
#define P2IE_               (0x002D)  /* Port 2 Interrupt Enable */
DEFC(   P2IE              , P2IE_)
#define P2SEL_              (0x002E)  /* Port 2 Selection */
DEFC(   P2SEL             , P2SEL_)
#define P2REN_              (0x002F)  /* Port 2 Resistor Enable */
DEFC(   P2REN             , P2REN_)

/************************************************************
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT3_R__          /* Definition to show that Module is available */
#define __MSP430_HAS_PORT4_R__          /* Definition to show that Module is available */

#define P3IN_               (0x0018)  /* Port 3 Input */
READ_ONLY DEFC( P3IN           , P3IN_)
#define P3OUT_              (0x0019)  /* Port 3 Output */
DEFC(   P3OUT             , P3OUT_)
#define P3DIR_              (0x001A)  /* Port 3 Direction */
DEFC(   P3DIR             , P3DIR_)
#define P3SEL_              (0x001B)  /* Port 3 Selection */
DEFC(   P3SEL             , P3SEL_)
#define P3REN_              (0x0010)  /* Port 3 Resistor Enable */
DEFC(   P3REN             , P3REN_)

#define P4IN_               (0x001C)  /* Port 4 Input */
READ_ONLY DEFC( P4IN           , P4IN_)
#define P4OUT_              (0x001D)  /* Port 4 Output */
DEFC(   P4OUT             , P4OUT_)
#define P4DIR_              (0x001E)  /* Port 4 Direction */
DEFC(   P4DIR             , P4DIR_)
#define P4SEL_              (0x001F)  /* Port 4 Selection */
DEFC(   P4SEL             , P4SEL_)
#define P4REN_              (0x0011)  /* Port 4 Resistor Enable */
DEFC(   P4REN             , P4REN_)

/************************************************************
* DIGITAL I/O Port5 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT5_R__          /* Definition to show that Module is available */

#define P5IN_               (0x0030)  /* Port 5 Input */
READ_ONLY DEFC( P5IN           , P5IN_)
#define P5OUT_              (0x0031)  /* Port 5 Output */
DEFC(   P5OUT             , P5OUT_)
#define P5DIR_              (0x0032)  /* Port 5 Direction */
DEFC(   P5DIR             , P5DIR_)
#define P5SEL_              (0x0033)  /* Port 5 Selection */
DEFC(   P5SEL             , P5SEL_)
#define P5REN_              (0x0012)  /* Port 5 Resistor Enable */
DEFC(   P5REN             , P5REN_)

/************************************************************
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT7_R__        /* Definition to show that Module is available */
#define __MSP430_HAS_PORT8_R__        /* Definition to show that Module is available */
#define __MSP430_HAS_PORTA_R__        /* Definition to show that Module is available */

#define P7IN_               (0x0038)  /* Port 7 Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFC( P7IN           , P7IN_)
#endif
#define P7OUT_              (0x003A)  /* Port 7 Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P7OUT             , P7OUT_)
#endif
#define P7DIR_              (0x003C)  /* Port 7 Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P7DIR             , P7DIR_)
#endif
#define P7SEL_              (0x003E)  /* Port 7 Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P7SEL             , P7SEL_)
#endif
#define P7REN_              (0x0014)  /* Port 7 Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P7REN             , P7REN_)
#endif

#define P8IN_               (0x0039)  /* Port 8 Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFC( P8IN           , P8IN_)
#endif
#define P8OUT_              (0x003B)  /* Port 8 Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P8OUT             , P8OUT_)
#endif
#define P8DIR_              (0x003D)  /* Port 8 Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P8DIR             , P8DIR_)
#endif
#define P8SEL_              (0x003F)  /* Port 8 Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P8SEL             , P8SEL_)
#endif
#define P8REN_              (0x0015)  /* Port 8 Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P8REN             , P8REN_)
#endif

#define PAIN_               (0x0038)  /* Port A Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFW( PAIN           , PAIN_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    READ_ONLY DEFXC                   P7IN;
    READ_ONLY DEFXC                   P8IN;
  };
  READ_ONLY DEFXW                     PAIN;
} @ 0x0038;
#endif
#define PAOUT_              (0x003A)  /* Port A Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PAOUT             , PAOUT_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P7OUT;
    DEFXC                             P8OUT;
  };
  DEFXW                               PAOUT;
} @ 0x003A;
#endif
#define PADIR_              (0x003C)  /* Port A Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PADIR             , PADIR_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P7DIR;
    DEFXC                             P8DIR;
  };
  DEFXW                               PADIR;
} @ 0x003C;
#endif
#define PASEL_              (0x003E)  /* Port A Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PASEL             , PASEL_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P7SEL;
    DEFXC                             P8SEL;
  };
  DEFXW                               PASEL;
} @ 0x003E;
#endif
#define PAREN_              (0x0014)  /* Port A Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PAREN             , PAREN_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P7REN;
    DEFXC                             P8REN;
  };
  DEFXW                               PAREN;
} @ 0x0014;
#endif

/************************************************************
* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT9_R__        /* Definition to show that Module is available */
#define __MSP430_HAS_PORT10_R__       /* Definition to show that Module is available */
#define __MSP430_HAS_PORTB_R__        /* Definition to show that Module is available */

#define P9IN_               (0x0008)  /* Port 9 Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFC( P9IN           , P9IN_)
#endif
#define P9OUT_              (0x000A)  /* Port 9 Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P9OUT             , P9OUT_)
#endif
#define P9DIR_              (0x000C)  /* Port 9 Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P9DIR             , P9DIR_)
#endif
#define P9SEL_              (0x000E)  /* Port 9 Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P9SEL             , P9SEL_)
#endif
#define P9REN_              (0x0016)  /* Port 9 Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P9REN             , P9REN_)
#endif

#define P10IN_              (0x0009)  /* Port 10 Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFC( P10IN          , P10IN_)
#endif
#define P10OUT_             (0x000B)  /* Port 10 Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P10OUT            , P10OUT_)
#endif
#define P10DIR_             (0x000D)  /* Port 10 Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P10DIR            , P10DIR_)
#endif
#define P10SEL_             (0x000F)  /* Port 10 Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P10SEL            , P10SEL_)
#endif
#define P10REN_             (0x0017)  /* Port 10 Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFC(   P10REN            , P10REN_)
#endif

#define PBIN_               (0x0008)  /* Port B Input */
#ifndef __IAR_SYSTEMS_ICC__
READ_ONLY DEFW( PBIN           , PBIN_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    READ_ONLY DEFXC                   P9IN;
    READ_ONLY DEFXC                   P10IN;
  };
  READ_ONLY DEFXW                     PBIN;
} @ 0x0008;
#endif
#define PBOUT_              (0x000A)  /* Port B Output */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PBOUT             , PBOUT_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P9OUT;
    DEFXC                             P10OUT;
  };
  DEFXW                               PBOUT;
} @ 0x000A;
#endif
#define PBDIR_              (0x000C)  /* Port B Direction */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PBDIR             , PBDIR_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P9DIR;
    DEFXC                             P10DIR;
  };
  DEFXW                               PBDIR;
} @ 0x000C;
#endif
#define PBSEL_              (0x000E)  /* Port B Selection */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PBSEL             , PBSEL_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P9SEL;
    DEFXC                             P10SEL;
  };
  DEFXW                               PBSEL;
} @ 0x000E;
#endif
#define PBREN_              (0x0016)  /* Port B Resistor Enable */
#ifndef __IAR_SYSTEMS_ICC__
DEFW(   PBREN             , PBREN_)
#endif

#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
  struct
  {
    DEFXC                             P9REN;
    DEFXC                             P10REN;
  };
  DEFXW                               PBREN;
} @ 0x0016;
#endif
              
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
#define __MSP430_HAS_SVS__            /* Definition to show that Module is available */

#define SVSCTL_             (0x0056)  /* SVS Control */
DEFC(   SVSCTL            , SVSCTL_)
#define SVSFG               (0x01)    /* SVS Flag */
#define SVSOP               (0x02)    /* SVS output (read only) */
#define SVSON               (0x04)    /* Switches the SVS on/off */
#define PORON               (0x08)    /* Enable POR Generation if Low Voltage */
#define VLD0                (0x10)
#define VLD1                (0x20)
#define VLD2                (0x40)
#define VLD3                (0x80)

#define VLDON               (0x10)
#define VLDOFF              (0x00)
#define VLD_1_8V            (0x10)

/************************************************************
* SD16_A4 - Sigma Delta 16 Bit
************************************************************/
#define __MSP430_HAS_SD16_A4__        /* Definition to show that Module is available */

#define SD16INCTL0_         (0x00B0)  /* SD16 Input Control Register Channel 0 */
DEFC(   SD16INCTL0        , SD16INCTL0_)
#define SD16INCTL1_         (0x00B1)  /* SD16 Input Control Register Channel 1 */
DEFC(   SD16INCTL1        , SD16INCTL1_)
#define SD16INCTL2_         (0x00B2)  /* SD16 Input Control Register Channel 2 */
DEFC(   SD16INCTL2        , SD16INCTL2_)
#define SD16INCTL3_         (0x00B3)  /* SD16 Input Control Register Channel 3 */
DEFC(   SD16INCTL3        , SD16INCTL3_)
#define SD16PRE0_           (0x00B8)  /* SD16 Preload Register Channel 0 */
DEFC(   SD16PRE0          , SD16PRE0_)
#define SD16PRE1_           (0x00B9)  /* SD16 Preload Register Channel 1 */
DEFC(   SD16PRE1          , SD16PRE1_)
#define SD16PRE2_           (0x00BA)  /* SD16 Preload Register Channel 2 */
DEFC(   SD16PRE2          , SD16PRE2_)
#define SD16PRE3_           (0x00BB)  /* SD16 Preload Register Channel 3 */
DEFC(   SD16PRE3          , SD16PRE3_)
#define SD16CONF0_          (0x00B7)  /* SD16 Internal Configuration Register 0 */
DEFC(   SD16CONF0         , SD16CONF0_)
#define SD16CONF1_          (0x00BF)  /* SD16 Internal Configuration Register 1 */
DEFC(   SD16CONF1         , SD16CONF1_)
                                      /* Please use only the recommended settings */

#define SD16CTL_            (0x0100)  /* Sigma Delta ADC 16 Control Register */
DEFW(   SD16CTL           , SD16CTL_)
#define SD16CCTL0_          (0x0102)  /* SD16 Channel 0 Control Register */
DEFW(   SD16CCTL0         , SD16CCTL0_)
#define SD16CCTL1_          (0x0104)  /* SD16 Channel 1 Control Register */
DEFW(   SD16CCTL1         , SD16CCTL1_)
#define SD16CCTL2_          (0x0106)  /* SD16 Channel 2 Control Register */
DEFW(   SD16CCTL2         , SD16CCTL2_)
#define SD16CCTL3_          (0x0108)  /* SD16 Channel 3 Control Register */
DEFW(   SD16CCTL3         , SD16CCTL3_)
#define SD16IV_             (0x0110)  /* SD16 Interrupt Vector Register */
DEFW(   SD16IV            , SD16IV_)
#define SD16MEM0_           (0x0112)  /* SD16 Channel 0 Conversion Memory */
DEFW(   SD16MEM0          

Написано более трёх лет назад

Answer 3

[PM1630]

Может попробовать в
LCDACTL = LCDON + LCD4MUX + LCDFREQ_128;
еще LCDSON воткнуть?
В мануале на микроконтроллер (стр. 298) пишут, что он отвечает за мигание, и все биты памяти с ним по AND работают.
И когда он в 0 (как в нашем случае) — все сегменты выключены.
Хотя я признаться не совсем понял как связаны мигание и выключенные/включенные сегменты.

Просто вероятность проблемы с отдельными сегментами IMHO не особо высока.
Соответственно копать предположительно стоит в области общих регистров.
А вообще в таких случаях можно еще например инкрементировать LCDACTL от 0 до FF каждые 10 секунд например — с расчетом, что какое-нибудь значение эту железяку удовлетворит :)
Хотя метод конечно варварский.

Comments

[ftp27]

Так тоже мерцает.
С LCDSON тоже пробовал. Там вообще какой то мрак, т.е. зажигается ряд сегментов и никак не реагирует на содержимое памяти, чтобы указать свой набор.

Answer 4

[PM1630]

Тогда в голову приходит только удалить включение низкого потребления — _BIS_SR(LPM3_bits) и вообще всё, оставив только голый индикатор.
Но это, как я понимаю, по всей видимости уже проверялось…

Answer 5

[PM1630]

Кстати, если основная программа выполняется в цикле (как это свойственно контроллерам) — возможно имеет смысл ввести какой-нибудь флаг, для однократного вывода на экран.

Вроде:
if (WriteOk == 0 ) then {
собственно вывод
WriteOk = 1;
}

Иначе возможно запись повторяется каждый цикл.