void uart_sc_mode(void) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
LPC_SYSCON->UARTCLKDIV &= ~0xff;
LPC_SYSCON->UARTCLKDIV |= 0x01;
LPC_IOCON->PIO0_19 &= ~(0x7f // clear 0-6 bits
| (1 << 10)); // clear 10 bit
LPC_IOCON->PIO0_19 |= (1 << 0) // TXD mode
| (1 << 10); // Open-drain mode
/* LPC_IOCON->PIO0_18 &= ~(0x7f // clear 0-6 bits
| (1 << 10)); // clear 10 bit
LPC_IOCON->PIO0_18 |= (1 << 0) // RXD mode
| (1 << 10); // Open-drain mode*/
LPC_IOCON->PIO0_17 &= ~(0x7f // clear 0-6 bits
| (1 << 10)); // clear 10 bit
LPC_IOCON->PIO0_17 |= 0x03; // SCLK mode
LPC_USART->SCICTRL |= 0x01; // Asynchronous half-duplex sc interface enable
LPC_USART->SCICTRL &= ~(3 << 1); // A NACK response is inhibited; T = 0
uart_sc_mode_config(SystemFrequency, 3570000, 372);
LPC_USART->IER = IER_RBR | IER_RLS;
}
void uart_sc_mode_config(uint32_t sys_clk, uint32_t Freq, uint32_t scale) {
uint32_t divider = ( ( ( sys_clk * 2 ) / Freq ) + 1 ) >> 1;
NVIC_DisableIRQ(UART_IRQn);
LPC_USART->LCR &= ~0x9f;
LPC_USART->LCR |= ( 3 << 0 ) // 8 bit
| ( 0 << 2 ) // 1 stop bit
| ( 1 << 3 ) // parity enable
| ( 1 << 4 ) // even parity
| ( 1 << 7 ); // DLAB = 1
LPC_USART->DLL &= ~0xff;
LPC_USART->DLM &= ~0xff;
LPC_USART->DLM = ( divider >> 8 ) & 0xff;
LPC_USART->DLL = divider & 0xff;
LPC_USART->LCR &= ~( 1 << 7 ); // DLAB = 0
LPC_USART->FCR |= ( 1 << 0 ) // enable access to the other field in register
| ( 1 << 1 ) // enable and clear RxBuff
| ( 1 << 2 ) // enable and clear TxBuff
| ( 0 << 6 ); // interrupt after every recieve byte
LPC_USART->OSR &= ~( 0x3fff );
LPC_USART->OSR = ( scale - 1 ) << 4;
LPC_USART->SCICTRL &= ~( ( 0xff << 8 ) | ( 0x07 << 5 ) );
LPC_USART->SCICTRL |= ( 0xff << 8 ) | ( 0x07 << 5 );
NVIC_EnableIRQ(UART_IRQn);
}
void
UART_IRQHandler( void )
{
timer0_stop();
timer0_reset();
if ( ( LPC_USART->IIR >> 1 ) & IIR_RDA ) {
g_UartMsg.buffer[g_UartMsg.byteCount++] = LPC_USART->RBR;
}
timer0_start(TIMEOUT_DEFAULT_BYTE, g_etu2ticks);
}